High linearity and high efficiency are required for power amplification circuits used in wireless communication systems. Particularly, recent multivalued digital modulation communication systems or the like often process a signal whose average amplitude and maximum amplitude are largely different. When amplifying such a signal using an existing power amplification circuit, the operating point of this power amplification circuit is set to amplify the signal to the maximum amplitude without distortion. Therefore, there is only a little time for the circuit to operate at near the saturation output power where relatively high efficiency can be maintained, and the efficiency of the power amplification circuit is low in general.
A solution to the above problem is disclosed in Patent Literature 1. Patent Literature 1 discloses the configuration of a Doherty amplification circuit that improves the power efficiency while maintaining the linearity. The Doherty amplification circuit includes a splitter that splits an input signal, a carrier amplifier that linearly amplifies one split signal, a peak amplifier that non-linearly amplifies the other split signal, and a combiner that combines output signals of the carrier amplifier and the peak amplifier. This Doherty amplification circuit thereby achieves high efficiency while maintaining the linearity. Further, this Doherty amplification circuit achieves downsizing by forming the carrier amplifier and the peak amplifier by transistors in one package.
Recently, Doherty amplification circuits with various operating characteristics like symmetrical type to extended type have been used as power amplification circuits. Thus, it is demanded to enhance the efficiency by reducing design man-hours and management and adjustment man-hours when designing and manufacturing such various types of Doherty amplification circuits.
Non Patent Literature 1 discloses an extended Doherty amplification circuit in which the sizes of transistors respectively forming a carrier amplifier and a peak amplifier and the relative position of the carrier amplifier and the peak amplifier are fixed. Patent Literature 2 discloses the configuration of a bias circuit that appropriately absorbs the variation of elements without degrading the high frequency characteristics.